1. Field of the Invention
The present invention is related to an error correction code generator, and more particularly, to an error correction code generator that uses an additional static random access memory (SRAM) or a multi-symbol encoder to improve the encoding efficiency thereof.
2. Description of Related Art
Traditionally, in a process for generating error correction codes, such as in the encoding process executed before recoding data on a digital versatile disc (DVD), the source data are usually pre-stored in a dynamic random access memory (DRAM). In the conventional DRAM, the stored data are usually addressed by the row and column addresses, and the DRAM is divided into multiple memory blocks according to the row and column addresses.
When the error correction code generator accesses the data stored in the DRAM, a row address and a column address are sent to the DRAM to indicate which data to be accessed. However, in order to make the data access more efficient, the conventional DRAM generally has a page-mode access function. In other words, if the data to be accessed have the same row address, i.e. they have the same memory page, the error correction code generator only needs to send the row; address when accessing the first data. The following data can be accessed just by sending the column addresses.
Furthermore, the DRAM only charges the memory blocks with the same row address when activating those memory blocks. Hence, every time the error correction code generator tries to access data with a different row address, it not only needs to send a row address but also to wait for a predetermined charge time. Thus, if the number of the row address switching of the data to be accessed increases, the access efficiency of the DRAM will decrease considerably.
In a conventional process for generating error correction codes, such as a process for generating parity of outer codes (PO codes) of Reed-Solomon product code (RSPC), accessing data blocks with different row addresses is often necessary. As a result, it needs to switch the new row address and wait for the predetermined charge time to access the data in different row addresses and the efficiency for generating the error correction codes is limited. Hence, the conventional process for generating error correction codes will consume a lot of time.
Please refer to FIG. 1, which is a conventional data structure for the Reed-Solomon product code. The conventional data structure includes three blocks, which are composed of multiple sub-blocks. Each of the sub-blocks represents a symbol of the operation of the error correction code and includes a byte of data. The sub-blocks are respectively marked as {Bi, j, i=0-207, j=0-181}.
The block at i=0-191 and j=0-171 is the scrambled source data; the block at i=192-207 and j=0-171 is the PO codes of Reed-Solomon product code; and the block at i=0-207 and j=172-181 is the parity of inner codes (PI codes) of Reed-Solomon product code.
The PO codes are the vertical parity codes of the source data. For example, the PO code of the PO column with i=0, B0-191, 0, is B192-207, 0. The PI codes are the horizontal parity codes of the source data. For example, the PI code of the PI row with j=0, B0, 0-171, is B0, 172-181.
Please refer to FIG. 2, which is a schematic diagram for illustrating the arrangement of the scrambled source data in the DRAM. Before encoding, the conventional error correction code generator generates a sequence of scramble bytes in advance to scramble the source data received from the host. Then, it stores the scrambled source data into the DRAM. Finally, the error correction code generator encodes the scrambled source data according to the Reed-Solomon product code.
By comparing FIG. 1 with FIG. 2, the stored DRAM addresses of the scrambled source data are shown. It is noted that the storage unit of the DRAM is “word”, which is equal to two bytes in this case. The order of storing the scrambled source data is (B0,0, B0,1, . . . B0,171, B1,0, . . . ).
According to the order of storing the scrambled source data, the row addresses of the source data for generating the PO codes of Reed-Solomon product code are frequently switched. Hence, in the process for generating the PO codes, the efficiency of conventional error correction code generator is low (the following description is directed to this question).
Please refer to FIG. 3, which is a block diagram of a conventional error correction code generator. The conventional error correction code generator 30 includes a first memory (DRAM) 31, a multiplexer 32 and an encoder 33. In the process of encoding, the host sends source data to the error correction code generator 30. Then, the error correction code generator 30 scrambles the source data and stores the scrambled source data into the first memory 31.
Then, the error correction code generator 30 accesses the scrambled source data stored in the first memory 31 column by column for generating the PO codes. However, as shown in FIG. 2, the storage unit of first memory 31 is “word”. Hence, two bytes of the data are read from first memory each time, and the multiplexer 32 selects the required byte of these two bytes and passes it to the encoder 33 for encoding.
Please refer to FIG. 2 again. According to the encoding structure and method described above, the operation of the vertical encoding should be executed 172 times to complete the total process for generating the PO codes. However, in order to execute the operation of the vertical encoding, e.g. encoding the data in B0-191,0 to generate the corresponding PO code in B192-207, the data accessing operation with row address switching should be performed 135 times and the data accessing operation without row address crossing should be performed 57 times.
Therefore, to complete the whole process for generating the PO codes, it totally performs 172×135=23220 times of the data access with row address switching and 172×57=9804 times of the data access without row address switching. Since the data access with row address switching is more time-consuming and this encoding method needs to access data mostly with row address switching, this encoding structure is inefficient and consumes a lot of time.
Accordingly, as discussed above, the prior art still has some drawbacks that could be improved. The present invention aims to resolve the drawbacks in the prior art.